The DVB (Digital Video Broadcast) standard provides for transmission of encoded television signals. To decode these signals a number of steps have to be performed, which include de-interleaving of the transmitted signals. De-interleaving involves rearrangement of data units, so that they their relative position in an output sequence differs from that in an input sequence in which the data units occur during transmission. De-interleaving is typically implemented by writing of data units of the received signal into a memory and reading of the data units from the memory in a sequence other than the sequence in which that data was written. When the data units are stored in an addressable memory, de-interleaving is controlled by the selection of addresses that are used for this purpose.
The DVB standard defines an address sequence that can be used for this purpose. The definition involves three sequences of numbers. The numbers of the first sequence are denoted by R′i, wherein i is an index that distinguishes different positions in the sequence. The numbers of the second sequence are denoted by Ri and the numbers of the third sequence are denoted by Hi. The DVB standard defines a recursive algorithm by which each successive value R′i in the first sequence can be computed from a preceding value R′i−1. This algorithm involves a shift of the binary representation of R′i−1 and the addition of a bit value that is computed as a logic function of selected ones of the bits of the binary representation of R′i−1. Next, the DVB standard defines a mapping that maps values R′1 of the first sequence to values Ri in the second sequence. Finally, the DVB standard defines the third sequence Hi as a copy of the second sequence from which all numbers have been omitted that exceed a threshold value. The DVB standard gives three definitions of this type, for use with three different block sizes.
Known implementations of this type of interleaving typically use a dedicated address computation circuit for computing the addresses Ri of the second sequence. Such a circuit contains a register that stores a current value of R′i of the first sequence, a first circuit for generating a next value R′i+1 from the value in the register and a second circuit for forming successive values Ri from successive values R′i in the register. When a plurality of sequences Ri has to be generated in parallel, a plurality of such circuits is needed in parallel, each with a register that holds the R′i value for a respective sequence.